Circuits requiring different clocks may be used, for example, in a synchronous system. When a plurality of clocks are used in the system, there is typically a request to synchronize input signals with the plurality of clocks to stably operate the system.
In this case, synchronization means that input signals are inputted to stably generate output signals that are synchronized with transitions of one or more clocks. A synchronization circuit is typically referred to as a circuit capable of stably synchronizing input signals with a plurality of clocks.
Assuming that a cycle of an input signal is T1, and a cycle of a clock is T2, in a flip-flop, the following relations are obtained. If T1>T2, the flip-flop receives the input signal to stably generate an output signal synchronized with a transition of the clock. To the contrary, if T1<T2, the input signal is not synchronized with the transition of the clock, so it may disappear.
In a case where an input signal is a pulse signal with a long cycle synchronized with a transition of a first clock, the input signal may become synchronized with a transition of a second clock with a short cycle, which also has a frequency higher than the first clock, thus generating an output signal. Therefore, the input signal can be prevented from disappearing. This is, because the cycle of the input signal is longer than that of the second clock. In other words, the input signal meets the transition of the second clock (e.g., a low-high transition) more than once when it is at a high level.
However, when the input signal is a pulse signal with a short cycle synchronized with the transition of the first clock, but not synchronized with the transition of the second clock with a long cycle and a low frequency, the input signal may disappear. This is, because the input signal may not meet the transition of the second clock more than once when it is at a high level.
Accordingly, a synchronization circuit for stably generating an output signal by synchronizing an input signal with the transition of the first clock and the transition of the second clock is desired.